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MAX17021 Evaluation Kit
down), the protection circuitry sets the fault latch to
prevent the controller from restarting. To clear the fault
latch and reactivate the MAX17021, toggle SHDN or
cycle V DD power.
DPRSLPVR SW2 (2, 9), PSI SW2 (3, 8)
DPRSLPVR and PSI together determine the operating
mode, as shown in Table 4. The MAX17021 will be
forced into full-phase pulse-skipping mode during start-
up and while in boot mode, and forced into full-phase
PWM mode during the transition from boot mode to VID
mode and during soft-shutdown.
DPRSTP , SW2 (5, 6)
This 1V logic input signal together with the DPRSLPVR
signal selects between the nominal and “slow” (quarter
of nominal rate) slew rates. When DPRSTP and
Table 6. PGDIN
DPRSLPVR are forced high, the slew rate is reduced to
a quarter of the nominal slew rate.
PGDIN, SW2 (4, 7)
PGDIN indicates the power status of other system rails
and is used for power-supply sequencing. After power-
up to the boot voltage, the output voltage remains at
V BOOT , CLKEN remains high, and PWRGD remains low
as long as the PGDIN stays low. When PGDIN is pulled
high, the output transitions to selected VID voltage, and
CLKEN is pulled low. If the system pulls PGDIN low
during normal operation, the MAX17021 immediately
drives CLKEN high, pulls PWRGD low, and slews the
output to the boot voltage (using 2-phase pulse-skip-
ping mode). The controller remains at the boot voltage
until PGDIN goes high again, SHDN is toggled, or the
V DD is cycled.
SW2 (4, 7)
Off
On*
*Default position.
PGDIN PIN
Connected to GND
Connected to VDD
MAX17021 OUTPUT
VOUT remains at the boot voltage. CLKEN remains high, and PWRGD
remains low.
VOUT transitions to selected VID voltage, and CLKEN is pulled low.
8
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